The present invention relates to a receiver arrangement responsive to an incoming analog signal and forming a digital representation thereof and, more particularly, to a baseband receiver including a dual-port digital-to-analog (DAC) converter for simultaneous use in both the I- and Q-rails of the receiver.
In a variety of communication systems the receiver portion is configured to process incoming analog signals into a digital representation for further processing in DSPs and the like. Wireless receivers, commonly used in today""s cellular communication market, are exemplary of this type of analog-to-digital (ADC) receiver. In a wireless receiver, the antenna picks up a transmitted radio frequency (RF) analog signal which is down-converted (either directly or first through an IF stage) to baseband for further signal processing. Typically, the final down-conversion includes the separation of the in-phase (I) and quadrature (Q) components, where the I and Q components are then processed (i.e., digitized) along separate signal paths. A problem with such an arrangement is that a duplicate number of components are required for signal processingxe2x80x94one set for the I component and a separate set for the Q componentsxe2x80x94resulting in a relatively large sized receiver that consumes a significant amount of power. Both of these characteristics are undesirable for a wireless receiver, which is required to be portable (e.g., hand-held) and operate on a battery power supply. U.S. Pat. No. 5,864,310 issued to H. Khorramabadi on Jan. 26, 1999 is exemplary of one such receiver arrangement (for a wireless receiver in particular), which utilizes a pair of flash analog-to-digital converters (ADCs)xe2x80x94one for the I rail component and one for the Q rail. The duplication of hardware results in the ADC portion of the receiver requiring a relatively large of amount of space.
One attempt to address the power consumption problem is to use a successive approximation ADC in each signal path. Successive approximation ADCs comprise a comparator, a digital-to-analog converter (DAC), and a successive approximation register. Such a circuit is able to operate with a single-ended or differential current or voltage source, thus significantly reducing power requirements over prior arrangements. While the successive approximation ADC does alleviate some of the power consumptions problems of the prior art, the size of the receiver remains quite large.
An exemplary solution to the size problem is to utilize a single set of components to perform the analog-to-digital conversion and include a switch to alternate between digitizing the I component and the Q component. That is, xe2x80x9csharexe2x80x9d the hardware by switching between the two rails. While this arrangement does provide for a savings on the space required for the conversion circuitry, an excessive amount of power is required to maintain the switching speed at a rate sufficient to provide accurate output data.
Thus, a need remains in the art for a baseband receiver using ADC processing that provides sufficient conversion throughput without incurring either the size or power penalties associated with the prior art.
The need remaining in the prior art is addressed by the present invention, which relates to a receiver arrangement responsive to an incoming analog signal and forming a digital representation thereof and, more particularly, to a baseband receiver including a dual-port digital-to-analog (DAC) converter for simultaneous use in both the I- and Q-rails of the receiver.
In accordance with a preferred embodiment of the present invention, the baseband receiver maintains separate I and Q signal paths, a successive approximation analog-to-digital converter (ADC) technique to process the received analog components. The successive approximation ADC in the receiver of the present invention comprises separate sample-and-hold circuits, comparators and successive approximation registers (SARs) on each signal path, as in the prior art. In a departure from the prior art, a single dual-port digital-to-analog converter (DAC) is used to simultaneously process both the received I and Q signal components. More particularly, the outputs from both SARs are applied as separate inputs to the dual-port DAC, where the separate outputs from the dual-port DAC are fed back as xe2x80x9cerror signalxe2x80x9d inputs to the respective comparators along the I and q signal paths. The dual-port DAC includes two separate sets of switches across a precision resistor ladder so that the same resistor ladder is used to simultaneously process the pair of input digital signals and generate as an output a pair of analog signals.
Advantageously, the dual-port DAC provides a significant size saving over using a separate pair of DACs (one for each signal path), since a dual-port DAC is approximately the same size as a conventional DAC. Further, since the dual-port DAC includes a single resistor ladder and reference potential source, it consumes approximately the same amount of power as a conventional DAC. A savings of approximately 50% in both size and power is thus achieved by using a dual-port DAC in a baseband receiver in accordance with the present invention.
Other and further advantages of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.